1. Field of the Invention
The present invention relates to silicon carbide (hereinafter referred to as SiC) semiconductor device that uses SiC as a semiconductor material, in particular, a voltage driven-type (MOS type power) SiC semiconductor device having a trench gate structure such as a Metal Oxide Semiconductor Field Effect Transistor (hereinafter referred to as MOSFET) or an Insulated Gate Bipolar Transistor (hereinafter referred to as IGBT), and a method for manufacturing the same.
2. Related Art
A SiC semiconductor material has high insulation breakdown field strength because the SiC semiconductor material has a large band gap in comparison with a silicon semiconductor material. An on-resistance is a resistance when a semiconductor device is in conduction. For example, an on-resistance of the SiC semiconductor device referred to as 4H type that is widely used can be suppressed to a several hundredth part of an on-resistance of a silicon semiconductor device because the on-resistance is in inverse proportion to the third power of the insulation breakdown field strength. Further, the SiC semiconductor device also has a large specific thermal conductivity characteristic that makes it easy to radiate heat. Therefore, the SiC semiconductor device is highly expected to be used as a low-loss power semiconductor device for the next generation. In recent years, the quality of SiC wafers (semiconductor substrate) has improved and also SiC wafers having a large diameter have been developed, and thus there has been active development of SiC semiconductor devices such as MOSFETs, Bipolar Transistors and Junction type Field Effect Transistors (JFETs) in which the characteristics of the SiC semiconductor devices exceed those of the silicon semiconductor devices substantially. MOSFETs especially have a feature of high speed switching in comparison with bipolar devices in which both electrons and holes contribute to conduction, because MOSFETs not only have lower cost gate driving circuits due to being voltage driven devices but also allow charge carriers to be swept out of the device without needing a swept time in a turn-off state, due to being majority carrier devices with only electrons or holes in which there is no storage of the carrier in conduction.
FIG. 9 illustrates a cross-sectional structure of a unit cell of a conventional and generic vertical-trench U-shape Metal Oxide Semiconductor Field Effect Transistor (hereinafter referred to as a conventional and generic UMOSFET). After sequentially forming a high-resistance n-type drift layer 22 and a p-type base layer 23 on a low-resistance n-type SiC semiconductor substrate (a drain layer) 21 by epitaxial SiC growth, an n+-type source region 24 is formed by ion implantation into the surface of the p-type base layer 23. A gate trench 25 is formed in such a SiC wafer 30. A gate oxide film 26, a gate electrode 27, a source/base electrode 28 and a drain electrode 29 are formed sequentially, and the wafer is completed.
In an off-state where the source/base electrode 28 is grounded and a large enough negative bias is applied to the gate electrode 27 for the off-state, holes are induced and stored in a region of the base layer 23 adjacent to an interface between the gate oxide film 26 and the base layer 23 interposed between the source region 24 and the drift layer 22. Thus, no current flows, because a pathway of electrons being employed as a conduction carrier is interrupted. When a positive high voltage is applied to the drain electrode 29, depletion layers are spread in both the base layer 23 and the drift layer 22, and the high voltage is maintained in a suppressed low leakage current-state because a junction between the base layer 23 and the drift layer 22 is in a reverse bias-state.
In an on-state where a positive bias large enough for the on-state is applied to the gate electrode 27, electrons are induced in the region (an inversion layer) of the base layer 23 adjacent to an interface between the gate oxide film 26 and the base layer 23 interposed between the source region 24 and the drift layer 22. Electrons employed as a conduction carrier flow sequentially between the source/base electrode 28, the source region 24, the inversion layer (not illustrated), the drift layer 22, the substrate 21 and the drain electrode 29.
Regarding a resistance in the on-state, a generic Double-Implanted Metal Oxide Semiconductor Field Effect Transistor (hereinafter referred to as a general DIMOSFET) shown in FIG. 10 has two resistances structurally added, that is, the first resistance is an accumulation one, in that electrons move over a neighborhood of an interface between a drift layer 32 and a gate oxide film 36, and the second resistance is a JFET one that occurs readily due to the drift layer 32 that is interposed between the base layers 33 of both sides when electrons flow from a neighborhood of the gate oxide film 36 in the drift layer 32 towards a drain layer beneath the drift layer 32. However, the conventional and generic UMOSFET shown in FIG. 9 has a feature whereby these two resistances do not occur. Therefore, when a pitch of unit cells is reduced in the generic DIMOSFET, the JFET resistance appears if the pitch of the unit cells is a critical distance or greater, and the on-resistance increases. On the other hand, the conventional and generic UMOSFET has a feature such that the on-resistance monotonically decreases as the pitch of unit cells becomes smaller. Especially, because it is necessary to reduce the pitch of unit cells by microfabrication for a MOSFET having a breakdown voltage of less than about 3 kV, due to a MOS channel resistance that cannot be ignored, it is preferable to use a vertical trench UMOSFET.
FIG. 11 shows a cross-sectional view showing a structure of a conventional and generic UMOSFET and electric field strength distribution diagrams showing the electric field strength in an off-state in a horizontal axis and a thickness direction of the substrate in a longitudinal axis in correspondence with this cross-sectional view regarding a PN junction part and a MOS structure part, each indicated in outline by a broken line. As can be seen from FIG. 11, the electric field strength applied to the oxide film (the SiO2 film) 26 on the bottom of the trench is very large. This depends on a difference between the relative permittivity (9.7 in the case of 4H—SiC) of SiC and the relative permittivity (3.8) of a SiO2 film. Further, the electric field strength applied to the oxide film at the corners of the trench becomes higher than that applied to the oxide film at the bottom of the trench due to the electric field concentration, although this is not illustrated in FIG. 11. Ideally, breakdown is caused in the SiC semiconductor device when the peak electric field strength of a p-n junction between the p-type base layer 23 and the n-type drift layer 22 shown in FIG. 11 reaches the insulation breakdown electric field strength of SiC. However, in the case of the conventional and generic UMOSFET, the oxide film (the SiO2 film) 26 at the bottom of the trench reaches the insulation breakdown electric field strength (about 10 MV/cm) before the peak electric field strength of the p-n junction between the base layer 23 and the drift layer 22 reaches the insulation breakdown electric field strength. Thus, there is a problem in that insulation breakdown in the conventional and generic UMOSFET is caused at a lower voltage than the theoretical breakdown voltage. Because the insulation breakdown electric field strength of a silicon semiconductor is 0.2 MV/cm that is two orders of magnitude smaller than that of the oxide film (the SiO2 film) of 10 MV/cm, the insulation breakdown of the silicon semiconductor is caused approximately in the p-n junction. However, because the insulation breakdown electric field strength of the SiC semiconductor (in the case of 4H—SiC) is 2 MV/cm, which is larger than that of the silicon semiconductor and that of the 4H—SiC semiconductor is only one order of magnitude different from that of the oxide film (the SiO2 film), a problem of the insulation breakdown of the oxide film (the SiO2 film) becomes significant.
For example, as one method of countermeasure for such a problem, J. Tan et al., IEEE Electron Dev. Lett., Vol. 19, p. 487-(1998) discloses that an aluminum or a boron ion implantation is carried out to the entire surface of an element using a mask just after forming a trench and then a UMOSFET is manufactured through a process of forming a p+ layer on only the bottom of the trench in which an impurity concentration is about 1×1018 cm−3 and a thickness is about 0.5 μm. Whereby, regarding an electric field strength distribution in a cross section perpendicular to the bottom of the trench, the very large electric field is absorbed by the p+ layer (an electric field relaxation layer) 40 on the bottom of the trench and the very large electric field is not applied to a oxide film (the SiO2 film) 26 as shown in FIG. 12 in spite of the very large electric field strength being applied to the oxide film (the SiO2 film) 26 in a conventional and generic structure as shown in FIG. 11. Thus, an improvement in breakdown voltage is realized by preventing the insulation breakdown in the oxide film (the SiO2 film) 26.
Japanese Patent No. 3711906 discloses a SiC semiconductor device where a p+ layer is formed along an inside surface of a trench and a surge-absorbing diode is formed thereby. In addition, Japanese Patent Laid-Open No. 2006-93186 discloses a SiC semiconductor device where a p++ contact layer of gate regions is formed on the bottom of a trench along an inner surface of the trench and whereby a voltage from outside can be supplied, so that a gate resistance is reduced and high speed switching operation becomes possible. Further, Japanese Patent Laid-Open No. 2004-6723 discloses a high breakdown voltage SiC semiconductor device where an excellent switch-off characteristic is obtained by a p-type gate layer formed on the bottom of a trench. Also, Japanese Patent Laid-Open No. 10-098188 discloses an invention that enables a high breakdown voltage by forming an electric field relaxation layer (p+ layer) of a conductivity type opposite to a drift layer in a drift layer underneath an insulation layer of a trench in a UMOSFET.
However, because the p+ layer on the bottom of the trench has to be grounded in the above Japanese Patent Laid-Open No. 10-098188, it is necessary to form an electrode for the p+ layer to be brought out on the surface. Therefore it is necessary to provide three electrode pads for a gate, a source and the p+ layer on the surface (an element-manufacturing surface). In a usual structure, there are only two electrode pads for the gate and the source on the surface. There is therefore a problem in the above Japanese Patent Laid-Open No. 10-098188 in that an active region in which a current flows in an element decreases due to the increased area of the pad for the p+ layer. Thus, there is a problem in that the on-resistance per unit area increases in the whole of a chip. Further, there is a problem in that more manufacturing steps are required, that is, the number of wire-bonding locations to connect electrodes to an external circuit is increased from two to three.